The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly not impliedly admitted as prior art against the present disclosure.
The present disclosure relates to memory systems and methods, and more specifically to detection and correction of timing signal drift in memory systems.
When a host device in a memory system reads data from a memory such as double data rate synchronous dynamic random access memory (DDR SDRAM), the host may use a timing signal (such as a data strobe sequence) provided by the memory in order to sample the data received from the memory. In particular, the host device may send a ‘Read’ command to the memory, requesting data contained at a particular address in the memory. After some delay period, the memory may send a data burst to the host device concurrently with a data strobe sequence. The host device may phase shift the data strobe sequence and sample the received data signal at every rising and falling edge that occurs within the data strobe sequence.
The delay period between the transmission of the ‘Read’ command by the host device and the return transmission of the data burst and the data strobe sequence by the memory may fluctuate due to factors such as variation in supply voltage, ambient temperature, and other system parameters. The host device may perform training during system startup in order to estimate this delay period, as well as various timing parameters used to sample the data signal when reading data from memory. However, the fluctuations in temperature and voltage can cause the timing of the data strobe sequence (i.e., timing signal) to drift, causing the estimated delay period and timing parameters to become invalid, and resulting in system errors during a data read.